The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification typically used for short distance communication. On an SPI bus, the circuits communicate according to a master-slaves scheme where the master monitors the communication, traditionally in duplex mode (or “full-duplex” mode as it is usually termed, that is to say a mode of communication in which the communication takes place simultaneously in both directions).
The half-duplex mode also exists, in which a single bidirectional line allows the exchange between the master and a slave, in a manner alternating in time.
FIGS. 1A and 1B represent the two commonest types of setup of an SPI bus.
The master peripheral (or device) M generates a clock signal on a clock line SCK and selects the slave peripheral (or device) with which it wishes to communicate through the use of a slave selection signal on a slave selection line SS, and the slave responds to the requests of the master.
At each clock tick the master and the slave exchange a bit via the master-output-slave-input MOSI pathway and the master-input-slave-output MISO pathway. After eight clock ticks the master has transmitted a byte to the slave and vice-versa. The frequency of the clock signal is adjusted according to characteristics specific to the peripherals.
FIG. 1A represents a configuration of a master device M and of n slave devices E1, E2, . . . En on an SPI bus in series, in which the peripherals are all linked “in a daisy chain,” one after the other.
In this series configuration, the SPI bus has 4 wires whatever the number of peripherals, but nonetheless exhibits numerous drawbacks. For example, the data received during the first clock pulses must be transmitted to other slaves during the other clock pulses so as finally to reach the last slave.
The slave devices which are not selected must therefore nevertheless be active during the communication, and an isolated failure of a slave device interrupts the entire chain.
The slave devices behave as a shift register in the chain as a whole, and execute a command contained in the last data received by order of the slave selection signal SS.
Furthermore, the frequency of the clock signal generated by the master is fixed and is limited by the speed of the slowest slave of the bus.
FIG. 1B represents a configuration of a master device M and of n slave devices E1, E2, . . . En on an SPI bus in parallel, in which the output-input MOSI and input-output MISO pathways are linked in parallel to all the slave devices E1-En.
In this parallel configuration, each slave can be selected via a slave selection line SS1, SS2, SSn which is respectively dedicated to it.
This configuration exhibits the advantage that the frequency of the clock signal can be optimized at each slave device ES1-ESn, and that the slaves that are not selected can remain inactive.
However, at least one pin of the master device M of FIG. 1B is dedicated to each slave device ES1-ESn, which may be problematic in the electrical layout. For example, the addressing of 32 slaves would require 32 pins, which may not be physically reasonable.
Moreover, whether it be in a series configuration or a parallel configuration, the setup is static and the chain cannot be enlarged dynamically during a communication.
Consequently it is desirable to improve the performance of data buses of the SPI serial peripheral interface type.